`timescale 1ns/100ps

module baudtester;

   
reg clock = 1, reset = 0, enable = 0;
wire [3:0] counter_out;

wire baud_clk;
wire [7:0] serial_data;
wire 	  serial_ready;

wire   serial_eop;
wire   serial_idle;
      
wire test_out;
   
reg rx = 1;

//divider div_test(.clk(clock), .clkout(test_out));
//tiny div_test(clock, test_out);

bdiv baud_generator(clock, baud_clk);

async_receiver rxtester(clock, baud_clk, rx, serial_ready, serial_data, serial_eop, serial_idle);
   
   
/* test data: */
initial begin: SERIAL /* Generated by mkserial */
//        $monitor ("%d\t res=%b", $time, rx);
	#104167 rx = 1; /* RX line starts HIGH */
	/* Character: 'H' */
	#104167 rx = 0; /* Start Bit */
	#104167 rx = 0; /* Bit 0 */
	#104167 rx = 0; /* Bit 1 */
	#104167 rx = 0; /* Bit 2 */
	#104167 rx = 1; /* Bit 3 */
	#104167 rx = 0; /* Bit 4 */
	#104167 rx = 0; /* Bit 5 */
	#104167 rx = 1; /* Bit 6 */
	#104167 rx = 0; /* Bit 7 */
	#104167 rx = 1; /* Stop Bit */
	#104167 rx = 1; /* RX line ends HIGH */
	/* Character: 'e' */
	#104167 rx = 0; /* Start Bit */
	#104167 rx = 1; /* Bit 0 */
	#104167 rx = 0; /* Bit 1 */
	#104167 rx = 1; /* Bit 2 */
	#104167 rx = 0; /* Bit 3 */
	#104167 rx = 0; /* Bit 4 */
	#104167 rx = 1; /* Bit 5 */
	#104167 rx = 1; /* Bit 6 */
	#104167 rx = 0; /* Bit 7 */
	#104167 rx = 1; /* Stop Bit */
	#104167 rx = 1; /* RX line ends HIGH */
	/* Character: 'l' */
	#104167 rx = 0; /* Start Bit */
	#104167 rx = 0; /* Bit 0 */
	#104167 rx = 0; /* Bit 1 */
	#104167 rx = 1; /* Bit 2 */
	#104167 rx = 1; /* Bit 3 */
	#104167 rx = 0; /* Bit 4 */
	#104167 rx = 1; /* Bit 5 */
	#104167 rx = 1; /* Bit 6 */
	#104167 rx = 0; /* Bit 7 */
	#104167 rx = 1; /* Stop Bit */
	#104167 rx = 1; /* RX line ends HIGH */
	/* Character: 'l' */
	#104167 rx = 0; /* Start Bit */
	#104167 rx = 0; /* Bit 0 */
	#104167 rx = 0; /* Bit 1 */
	#104167 rx = 1; /* Bit 2 */
	#104167 rx = 1; /* Bit 3 */
	#104167 rx = 0; /* Bit 4 */
	#104167 rx = 1; /* Bit 5 */
	#104167 rx = 1; /* Bit 6 */
	#104167 rx = 0; /* Bit 7 */
	#104167 rx = 1; /* Stop Bit */
	#104167 rx = 1; /* RX line ends HIGH */
	/* Character: 'o' */
	#104167 rx = 0; /* Start Bit */
	#104167 rx = 1; /* Bit 0 */
	#104167 rx = 1; /* Bit 1 */
	#104167 rx = 1; /* Bit 2 */
	#104167 rx = 1; /* Bit 3 */
	#104167 rx = 0; /* Bit 4 */
	#104167 rx = 1; /* Bit 5 */
	#104167 rx = 1; /* Bit 6 */
	#104167 rx = 0; /* Bit 7 */
	#104167 rx = 1; /* Stop Bit */
	#104167 rx = 1; /* RX line ends HIGH */
//        $stop;
        #104167;
        #104167;
        $finish;   
end /* Generated by mkserial */
/* end of test data */


// Clock generator
always
begin
   clock = 1'b1;
   #12.5;
   clock = 1'b0;
   #12.5;
end


   
initial begin: Init
   #0
   $display ("Init!\n");
//$monitor ("%d\t baudgen=%b", $time, baud_clk);
//$monitor ("rx=%b", rx);
//$display ("time\t clk reset enable counter");	
//$monitor ("%g\t %b   %b     %b      %b", $time, clock, reset, enable, counter_out);
//clock = 1;       // initial value of clock
//reset = 0;       // initial value of reset
//enable = 0;      // initial value of enable
//#200 reset = 1;    // Assert the reset
//#300 reset = 0;   // De-assert the reset
//#10 enable = 1;  // Assert enable
//#10000 enable = 0; // De-assert enable
end // block: Init


always
begin   
   @(posedge serial_ready)
   $display ("%d\t data=%b data_ascii=%c ready=%b", $time, serial_data, serial_data, serial_ready);
end


endmodule

/*
module baudmake(clk, max_tick);   
   input clk;
   output max_tick;

   wire   clk;
   wire   max_tick;
   
   
   reg [9:0] r_reg = 0;
   wire [9:0] r_next;

   always @(posedge clk) r_reg <= r_next;

   assign r_next = (r_reg==(261-1)) ? 0 : r_reg + 1;
   assign max_tick = (r_reg==(261-1)) ? 1'b1 : 1'b0;
endmodule
*/

module bdiv(clk, clkout);
   input clk;
   output clkout;

   wire   clk;
   wire   clkout;
      
   reg [10:0] count = 0;
   
   always @ (posedge clk)
     begin
	count <= count + 1;
	if (count == 521 - 1) count <= 0;
     end
   assign clkout = (count == 0);
endmodule


module async_receiver(clk, clk8, RxD, RxD_data_ready, RxD_data, RxD_endofpacket, RxD_idle);
input clk, clk8, RxD;
output RxD_data_ready;  // onc clock pulse when RxD_data is valid
output [7:0] RxD_data;

// We also detect if a gap occurs in the received stream of characters
// That can be useful if multiple characters are sent in burst
//  so that multiple characters can be treated as a "packet"
output RxD_endofpacket;  // one clock pulse, when no more data is received (RxD_idle is going high)
output RxD_idle;  // no data is being received

////////////////////////////
reg [1:0] RxD_sync_inv = 0;
always @(posedge clk) if(clk8) RxD_sync_inv <= {RxD_sync_inv[0], ~RxD};
// we invert RxD, so that the idle becomes "0", to prevent a phantom character to be received at startup

reg [1:0] RxD_cnt_inv = 0;
reg RxD_bit_inv = 0;

always @(posedge clk)
if(clk8)
begin
	if( RxD_sync_inv[1] && RxD_cnt_inv!=2'b11) RxD_cnt_inv <= RxD_cnt_inv + 2'h1;
	else 
	if(~RxD_sync_inv[1] && RxD_cnt_inv!=2'b00) RxD_cnt_inv <= RxD_cnt_inv - 2'h1;

	if(RxD_cnt_inv==2'b00) RxD_bit_inv <= 1'b0;
	else
	if(RxD_cnt_inv==2'b11) RxD_bit_inv <= 1'b1;
end

reg [3:0] state = 0;
reg [3:0] bit_spacing = 0;

// "next_bit" controls when the data sampling occurs
// depending on how noisy the RxD is, different values might work better
// with a clean connection, values from 8 to 11 work
wire next_bit = (bit_spacing==4'd10);

always @(posedge clk)
if(state==0)
	bit_spacing <= 4'b0000;
else
if(clk8)
	bit_spacing <= {bit_spacing[2:0] + 4'b0001} | {bit_spacing[3], 3'b000};

always @(posedge clk)
if(clk8)
case(state)
	4'b0000: if(RxD_bit_inv) state <= 4'b1000;  // start bit found?
	4'b1000: if(next_bit) state <= 4'b1001;  // bit 0
	4'b1001: if(next_bit) state <= 4'b1010;  // bit 1
	4'b1010: if(next_bit) state <= 4'b1011;  // bit 2
	4'b1011: if(next_bit) state <= 4'b1100;  // bit 3
	4'b1100: if(next_bit) state <= 4'b1101;  // bit 4
	4'b1101: if(next_bit) state <= 4'b1110;  // bit 5
	4'b1110: if(next_bit) state <= 4'b1111;  // bit 6
	4'b1111: if(next_bit) state <= 4'b0001;  // bit 7
	4'b0001: if(next_bit) state <= 4'b0000;  // stop bit
	default: state <= 4'b0000;
endcase

reg [7:0] RxD_data = 0;
always @(posedge clk)
if(clk8 && next_bit && state[3]) RxD_data <= {~RxD_bit_inv, RxD_data[7:1]};

reg RxD_data_ready, RxD_data_error = 0;
always @(posedge clk)
begin
	RxD_data_ready <= (clk8 && next_bit && state==4'b0001 && ~RxD_bit_inv);  // ready only if the stop bit is received
	RxD_data_error <= (clk8 && next_bit && state==4'b0001 &&  RxD_bit_inv);  // error if the stop bit is not received
end

reg [4:0] gap_count = 0;
always @(posedge clk) if (state!=0) gap_count<=5'h00; else if(clk8 & ~gap_count[4]) gap_count <= gap_count + 5'h01;
assign RxD_idle = gap_count[4];
reg RxD_endofpacket = 0;
always @(posedge clk) RxD_endofpacket <= clk8 & (gap_count==5'h0F);

endmodule